AD5673R/AD5677R

Data Sheet

Rev. 0 | Page 4 of 31

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE OUTPUT

Output Voltage4

2.4975

2.5025

V

Voltage Reference Temperature

Coefficient (TC)5, 6

2

5

ppm/°C

See voltage reference temperature coefficient

(TC) in the Terminology section

Output Impedance

0.04

Ω

Output Voltage Noise

13

µV p-p

0.1 Hz to 10 Hz

Output Voltage Noise Density

240

nV/√Hz

At ambient temperature (TA), f = 10 kHz,

CL = 10 nF, gain = 1 or 2

Load Regulation Sourcing

29

µV/mA

At TA

Load Regulation Sinking

74

µV/mA

At TA

Output Current Load Capability

±20

mA

VDD ≥ 3 V

Line Regulation

43

µV/V

At TA

Long-Term Stability Drift

77

ppm

After 1000 hours at 25°C

Thermal Hysteresis

125

ppm

First cycle

25

ppm

Additional cycles

LOGIC INPUTS

Input Current

±1

µA

Per pin

Input Voltage

Low, VIL

0.3 × VLOGIC

V

1.62 V ≤ VLOGIC ≤ 3.3 V

0.25 × VLOGIC

V

3.3 V ≤ VLOGIC ≤ 5.5 V

High, VIH

0.7 × VLOGIC

V

Pin Capacitance

4

pF

LOGIC OUTPUTS (SDA)

Output Voltage

Low, VOL

0.4

V

Output low current (IOL) = 3 mA

High, VOH

VLOGIC − 0.4

V

Output high current (IOH) = −3 mA

Floating State Output Capacitance

9

pF

POWER REQUIREMENTS

VLOGIC

1.62

5.5

V

1. 8 V logic compatibility

VLOGIC Supply Current (ILOGIC)

3

µA

Power-on, −40°C to +105°C

3

µA

Power-on, −40°C to +125°C

3

µA

Power-down, −40°C to +105°C

3

µA

Power-down, −40°C to +125°C

VDD

2.7

5.5

V

Gain = 1

VREF + 1.5

5.5

V

Gain = 2

VDD Supply Current (IDD)

VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V

Normal Mode7

2.3

2.53

mA

Internal reference off, −40°C to +85°C

3.4

3.8

mA

Internal reference on, −40°C to +85°C

2.3

2.6

mA

Internal reference off

3.4

4.2

mA

Internal reference on

All Power-Down Modes8

2

3.4

µA

Power-down to 1 kΩ, −40°C to +85°C

2

5

µA

Power-down to 1 kΩ, −40°C to +105°C

2

11

µA

Power-down to 1 kΩ, −40°C to +125°C

1

DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =

VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.

2

VDD = 5 V. The device includes current limiting intended to protect the devices during temporary overload conditions. Junction temperature (TJ) can be exceeded

during current limit. Operation above the specified maximum operation junction temperature can impair device reliability.

3

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.

4

Initial accuracy presolder reflow is ±750 µV. Output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.

5

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.

6

Voltage reference temperature coefficient is calculated as per the box method. See the voltage reference temperature coefficient (TC) definition in the Terminology

section for further information.

7

Interface inactive. All DACs active. DAC outputs unloaded.

8

All DACs powered down.