AD5674/AD5674R/AD5679/AD5679R

Data Sheet

Rev. B | Page 24 of 32

Table 10. Command Definitions

Command

C3

C2

C1

C0

Description

0

0

0

0

No operation

0

0

0

1

Write to Input Register n where n = 1 to 8, depending on the DAC selected from the

address bits in Table 11 (dependent on LDAC)

0

0

1

0

Update DAC Register n with contents of Input Register n

0

0

1

1

Write to and update DAC Channel n

0

1

0

0

Power down/power up the DAC

0

1

0

1

Hardware LDAC mask register

0

1

1

0

Software reset (power-on reset)

0

1

1

1

Internal reference setup register

1

0

0

0

Set up the daisy-chain enable (DCEN) register

1

0

0

1

Set up the readback register (readback enable)

1

0

1

0

Update all channels of the input register simultaneously with the input data

1

0

1

1

Update all channels of the DAC register and input register simultaneously with the input

data

1

1

0

0

Reserved

…

…

…

…

1

1

1

1

No operation, daisy-chain mode

Table 11. Address Commands

Channel Address[3:0]

Selected Channel

A3

A2

A1

A0

0

0

0

0

DAC 0

0

0

0

1

DAC 1

0

0

1

0

DAC 2

0

0

1

1

DAC 3

0

1

0

0

DAC 4

0

1

0

1

DAC 5

0

1

1

0

DAC 6

0

1

1

1

DAC 7

1

0

0

0

DAC 8

1

0

0

1

DAC 9

1

0

1

0

DAC 10

1

0

1

1

DAC 11

1

1

0

0

DAC 12

1

1

0

1

DAC 13

1

1

1

0

DAC 14

1

1

1

1

DAC 15

Figure 59. AD5679/AD5679R Input Shift Register Content

Figure 60. AD5674/AD5674R Input Shift Register Content

DB23 (MSB)

DB0 (LSB)

C3

C2

C1

C0

D11

D10

D9

D8

D15

D14

D13

D12

D7

D6

D5

D4

D3

D2

D1

D0

COMMAND BITS

ADDRESS BITS

DATA BITS

A3

A2

A1

A0

DB23 (MSB)

C3

C2

C1

C0

A3

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

COMMAND BITS

ADDRESS BITS

DATA BITS

DB0 (LSB)