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Power Integrations

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Power Integrations may make changes to its products at any time. Power Integrations has no liability arising from your use of any information, device or circuit

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SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A

PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. The products and applications illustrated herein (including circuits external to the

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Core Material

Bobbin

Winding Details

Winding Order

(pin numbers)

Primary

Inductance

Primary Resonant

Frequency

Leakage

Inductance

TRANSFORMER PARAMETERS

Ferroxcube P/N: PTS14/8-3F3, ungapped

8 pin P1408 surface mount B&B B-096 or

equivalent

Primary: 8T + 7T, 27 AWG,

5 V 4T, 4 x 28 AWG

7.5 V 2T, 4 x 28 AWG

Primary-1 (4-3), 7.5 V (7-8), 5 V (5-6)

Primary-2 (3-1)

434 µH ±25% @ 100 kHz

3.8 MHz (minimum)

1 µH (maximum)

Core Material

Bobbin

Winding Details

Winding Order

(pin numbers)

Inductance

INDUCTOR PARAMETERS

Epcos N87, P/N: B65755-J-R87, Gap for

A

2

8 pin P1408 surface mount B&B B-096 or

equivalent

Bias 26T, 34 AWG

5 V 6T, 2 x 28 AWG

7.5 V 12T, 28 AWG

20 V 40T, 34 AWG

7.5 V (7-6), 5 V (8-5), 20 V (1-2), Bias (4-3)

Pin (5-8): 16 µH ±10% @ 100 kHz

Table 3. Inductor Design Parameters.

Table 2. Transformer Design Parameters.

Key Design Points

• Zener VR1 safely limits the DRAIN voltage below

BV

• At zero load, maximum input voltage, the bias voltage

across C6 should be >8 V (12 V to 15 V under normal

conditions).

• The 5 V output is the regulated output. All other outputs

are derived from it.Therefore, tight transformer secondary

coupling and low PC board trace impedance from the 5

V output to the 7.5 V output are crucial to achieve good

cross-regulation.

• The transformer must reset completely under all line

and load conditions to prevent core saturation. The

gate capacitance of Q22 (with other parasitic circuit

capacitances), determines the minimum reset period. The

transformer core reset voltage also drives the secondary

synchronous rectifier Q22. Efficiency is maximized when

Q22conductionperiodismaximized. ThisQ22conduction

periodcanbeextendedbyaddingmorecapacitance(anR-C

snubber across the 5 V winding). The reset period should

be set to give as long a reset as possible when operating

at low-line (maximum duty cycle) while still guaranteeing

complete reset.

• Good layout practices should be followed:

- Locate C4, C5 and R3 close to U1 with grounds returned

to the SOURCE pin.

- Minimizetheprimaryandsecondaryloopareastoreduce

parasitic leakage inductance.

- LocateD21andQ22returnconnectionsveryclosetoeach

other to provide best cross-regulation between 5 V and

7.5 V.

Table 1. Worst Case Output Cross-Regulation - All Outputs Taken

from Minimum to Maximum Load.

Load

Range

(%)

5

36-72 20-100

7.5

36-72

0-100

7

36-72

100

Cross-Regulation (%)

-6 -5 -4 -3 -2 -1 0 1

2 3 4 5

6

7 8

Voltage

Range

(VDC)