TDA4887PS datasheet(21/68 Pages) PHILIPS

21 / 68 page

2001 Oct 19

Philips Semiconductors

Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

TDA4887PS

6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and

pedestal blanking). With a fast clamping pulse (transition between VCLI = 1.2 to 3.5 V and 3.5 to 1.2 V in less than

75 ns/V) no blanking will occur during input clamping.

For 75 ns/V < tr/f5 ≤ 280 ns/V the generation of the internal blanking pulse is uncertain. For tr/f5 > 280 ns/V the

internal blanking pulse will be generated.

If pin 5 is open-circuit, it will activate permanent input clamping and undefined blanking.

7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). With a completed I2C-bus

transmission in buffered mode, only the leading edge of a vertical blanking pulse activates an adjustment (see also

Section 7.10).

After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further

transmissions in direct or buffered mode are enabled.

I2C-bus transmissions in direct mode need no synchronization pulses.

8. Input voltages less than

−0.1 V can produce internal substrate currents which disturb the leakage currents at the

signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or with negative

voltage. Feeding clamping and blanking pulses via a resistor (several k

Ω) protects the pin from negative voltages.

9. Pin 11 should be used for output clamping and/or blanking. If pin 11 is open-circuit, it will activate permanent blanking

and output clamping.

10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below

input reference black level (see Fig.3).

11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 0.4% of

contrast range).

12.

An: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting.

An0: colour signal output amplitude in channel n = 1, 2 or 3 at maximum contrast setting and same gain setting.

13. When OSD fast blanking is active and OSD inputs OSD1, OSD2 and OSD3 are HIGH (VFBL > 1.7 V, VOSD(n) > 1.7 V)

the OSD colour signals will be inserted in front of the gain potentiometers. This ensures a correct grey scale of all

video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via the

I2C-bus.

The inserted black level change (

∆Vbl) due to brightness control is not affected by OSD fast blanking.

14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution

6.7% of OSD contrast range).

15. This pin can be used for subcontrast adjustment, beam current limiting and contrast modulation. Both the video and

OSD contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin

should be tied to a voltage of more than 5 V or decoupled with a capacitor (several nF) if not used.

16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution

0.4% of brightness range). When control bit BRI = 1 the internal gain dependent brightness control is switched off

and the feedback reference voltages (control bit FPOL = 0) or DAC output voltages for DC restoration (control bit

FPOL = 1) at the cathodes are shifted with brightness control.

17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3)

with nominal 0.7 V (p-p) input signal, at maximum contrast (subaddress 02H = FFH) and for any gain setting.

This voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore

∆Vbl (in percent)

is constant for any gain setting. The given values of

∆Vbl are valid only for video black levels higher than the minimum

output voltage level Vo(n)(min).

∆G

track

maximum of

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