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MP3435GL 데이터시트(PDF) 3 Page - Monolithic Power Systems

부품명 MP3435GL
상세설명  19A, 600kHz, 22V Output Range, Synchronous Boost Converter with Input Disconnect Function
PDF  26 Pages
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제조업체  MPS [Monolithic Power Systems]
홈페이지  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP3435GL 데이터시트(HTML) 3 Page - Monolithic Power Systems

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MP3435 – 19A, 600kHz, 22V SYNCHRONOUS BOOST WITH INPUT DISCONNECT
MP3435 Rev. 1.0
MonolithicPower.com
3
11/30/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin #
Name
Description
1, 2
OUT
Power output. Connect OUT to the high-side MOSFET (HS-FET)
’s drain.
3
TM
Internal test pin. Only use in product test mode. Float TM in application.
4
BST
Bootstrap. BST powers the HS-FET driver.
5
SOUT
Samples the output voltage and charges the BST capacitor. VDD is powered from
SOUT when VSOUT exceeds VIN.
6
EN
Regulator on/off control input. Pull this pin high to turn on the internal regulator circuit;
pull it low to turn off the regulator circuit. An input above the EN turn-on threshold
enables the IC to start switching. When the EN pin is not used, connect EN to the input
source (through a 100kΩ pull-up resistor if VIN > 5.5V) for automatic start-up. This pin can
also configure VIN UVLO. Do not leave EN floating.
7
GATE
Driver for the input disconnect MOSFET. If this pin is floating or connected to the input
MOSFET gate, an external current-sense resistor is required. Connect GATE to ground
to use the internal current-sense circuit. Do not pull GATE down to ground through a
resistor.
8
SENSE
Voltage sense. The voltage sensed between SENSE and IN determines the external
current-sense signal. Connect SENSE to IN if the internal current-sense function is
selected.
9, 20
SW
Power switch. Connect SW to the internal low-side MOSFET (LS-FET)
’s drain and the
internal, synchronous HS-FET source. Connect the power inductor to SW.
10, 17,
18, 19
PGND
Power ground.
11
IN
Input supply. IN must be locally bypassed.
12
VDD
Internal bias supply. Decouple the VDD pin
with a 2.2μF ceramic capacitor, placed as
close to VDD as possible.
13
COMP
Compensation. Connect a capacitor and resistor in series to the analog ground for loop
stability.
14
FB
Feedback input. The reference voltage (VREF) is 1.225V. Connect a resistor divider from
output to FB.
15
SS
Soft-start control. Connect a soft-start capacitor (CSS) to SS. CSS is charged with a
constant current. Leave SS disconnected if soft start is not used.
16
AGND
Analog ground.



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