Data Sheet

AD736

Rev. I | Page 13 of 20

APPLICATIONS

CONNECTING THE INPUT

The inputs of the AD736 resemble an op amp, with noninverting

and inverting inputs. The input stages are JFETs accessible at

Pin 1 and Pin 2. Designated as the high impedance input, Pin 2

is connected directly to a JFET gate. Pin 1 is the low impedance

input because of the scaling resistor connected to the gate of the

second JFET. This gate-resistor junction is not externally accessible

and is servo-ed to the voltage level of the gate of the first JFET,

as in a classic feedback circuit. This action results in the typical

8 kΩ input impedance referred to ground or reference level.

This input structure provides four input configurations as

shown in Figure 21, Figure 22, Figure 23, and Figure 24.

Figure 21 and Figure 22 show the high impedance configurations,

and Figure 23 and Figure 24 show the low impedance connections

used to extend the input voltage range.

AD736

COM

+VS

+VS

OUTPUT

CF

1MΩ

VOUTDC

CAV

CC

VIN

–VS

1

2

3

4

8

7

6

5

CAV

–VS

Figure 21. High-Z AC-Coupled Input Connection (Default)

AD736

COM

+VS

+VS

OUTPUT

VOUTDC

CAV

CC

VIN

–VS

1

2

3

4

8

7

6

5

CAV

CF

–VS

Figure 22. High-Z DC-Coupled Input Connection

AD736

COM

+VS

+VS

OUTPUT

VOUTDC

CAV

CC

VIN

–VS

1

2

3

4

8

7

6

5

CAV

CF

–VS

Figure 23. Low-Z AC-Coupled Input Connection

AD736

COM

+VS

+VS

OUTPUT

VOUTDC

CAV

CC

VIN

–VS

1

2

3

4

8

7

6

5

CAV

CF

–VS

Figure 24. Low-Z DC-Coupled Input Connection