93AA46SLASHP datasheet(7/22 Pages) MICROCHIP

7 / 22 page

 2004 Microchip Technology Inc.

DS20067J-page 7

93AA46/56/66

2.7

Write

The WRITE instruction is followed by 16 bits (or by 8

bits) of data which are written into the specified

address. After the last data bit is put on the DI pin,

CS must be brought low before the next rising edge

of the CLK clock. This falling edge of CS initiates the

self-timed auto-erase and programming cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the specified address has been written with the data

specified and the device is ready for another

instruction.

The write cycle takes 4 ms per word typical.

2.8

Erase All (ERAL)

The ERAL instruction will erase the entire memory array

to the logical “1” state. The ERAL cycle is identical to

the erase cycle except for the different opcode. The

ERAL cycle is completely self-timed and commences

at the falling edge of the CS. Clocking of the CLK pin is

not necessary after the device has entered the Self

Clocking mode. The ERAL instruction is ensured at 5V

± 10%.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

The ERAL cycle takes (8 ms typical).

2.9

Write All (WRAL)

The WRAL instruction will write the entire memory array

with the data specified in the command. The WRAL

cycle is completely self-timed and commences at the

falling edge of the CS. Clocking of the CLK pin is not

necessary after the device has entered the Self Clock-

ing mode. The WRAL command does include an auto-

matic ERAL cycle for the device. Therefore, the WRAL

instruction does not require an ERAL instruction but the

chip must be in the EWEN status. The WRAL instruction

is ensured at 5V

± 10%.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

The WRAL cycle takes 16 ms typical.

FIGURE 2-1:

SYNCHRONOUS DATA TIMING

CLK

(Read)

(Program)

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

TCSS

TDIS

TSV

TCSH

TCKL

TCKH

TDIH

TPD

TCZ

Status Valid

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