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SN74LVC166APWR 데이터시트(PDF) 20 Page - Texas Instruments |
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SN74LVC166APWR 데이터시트(HTML) 20 Page - Texas Instruments |
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20 / 24 page ![]() 8.4.2 Layout Example 1 2 3 4 5 6 7 16 15 14 13 12 11 10 SER A C D GND VCC SH/LD H G F E GND VCC QH B 0.1 F Unused input tied to GND Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused inputs tied to VCC CLK CLR 8 9 CLK INH Figure 8-3. Example Layout for the SN74LVC166A SN74LVC166A SCLSA15 – MAY 2024 www.ti.com 20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: SN74LVC166A |
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