25C160-SLASHP datasheet(11/22 Pages) MICROCHIP

11 / 22 page

 2004 Microchip Technology Inc.

DS21231D-page 11

25AA160/25LC160/25C160

FIGURE 3-7:

WRITE STATUS REGISTER TIMING SEQUENCE

3.7

Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

•A WRITE ENABLE instruction must be issued to

set the write enable latch

• After a byte write, page write, or Status register

write, the write enable latch is reset

•CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

3.8

Power On State

The 25XX160 powers on in the following state:

• The device is in low power Standby mode (CS = 1)

• The write enable latch is reset

• SO is in high-impedance state

• A low level on CS is required to enter active state

TABLE 3-3:

WRITE-PROTECT FUNCTIONALITY MATRIX

1011

12131415

765

instruction

data to Status register

High-impedance

SCK

234567

WPEN

WEL

Protected Blocks

Unprotected Blocks

Status Register

Protected

Writable

Low

Protected

Writable

Protected

High

Protected

Writable

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