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AM79C940JC/W 데이터시트(PDF) 92 Page - Advanced Micro Devices

부품명 AM79C940JC/W
상세설명  Media Access Controller for Ethernet (MACE??
PDF  144 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

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92
DC CHARACTERISTICS (Continued)
Notes:
1. VOH does not apply to open-drain output pins.
2. IIL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1.
IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.
IIL2 =TC, TDI, TCK, TMS.
3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.
4. IOZ applies to all three-state output pins and bi-directional pins.
5. Test not implemented to data sheet specification.
6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
7. During the activation of SLEEP:
–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR
and TDO.
–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:
DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.
–The following input pin has its internal pull-up and TTL level translator disabled: TC.
–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,
R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.
–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+
and DO.
–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.
–AWAKE and RWAKE are reset to zero. IDDSLEEP, with either AWAKE set or RWAKE set, will be much higher and its
value remains to be determined.
8. Parameter not tested.
9. For industrial temperature version, Max value is –150
µA.
10. For industrial temperature version, Max value is +150
µA.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VLTHS–
RXD Post-Squelch
Negative Threshold (Peak)
LRT = LOW
–156
–90
mV
VRXDTH
RXD Switching Threshold
(Note 4)
–35
35
mV
VTXH
TXD
± and TXD± Output
HIGH Voltage
DVSS = 0V
DVDD –0.6
DVDD
V
VTXL
TXD
± and TXD± Output
LOW Voltage
DVDD = +5V
DVSS
DVSS + 0.6
V
VTXI
TXD
± and TXD± Differential
Output Voltage Imbalance
–40
+40
mV
VTXOFF
TXD
± and TXD± Idle Output
Voltage
DVDD = +5V
40
mV
RTX
TXD
± Differential Driver Output
Impedance
(Note 8)
40
Ω
TXD
± Differential Driver Output
Impedance
(Note 8)
80
Ω



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