STPM01FTR datasheet(17/56 Pages) STMICROELECTRONICS

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STPM01

Theory of operation

17/56

8.3

∑∆ A/D Converters

The analog to digital conversion in the STPM01 is carried out using two first order

∑∆

converters. The device performs A/D conversions of analog signals on two independent

channels in parallel. The current channel is multiplexed as primary or secondary current

channel in order to be able to perform a tamper function, if it is enabled. The converted

∑∆

signals are supplied to the internal hardwired DSP unit, which filters and integrates those

signals in order to boost the resolution and to yield all the necessary signals for

computations.

∑∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a

rate determined by the sampling clock. In the STPM01, the sampling clock is equal to fCLK/4.

The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is

subtracted from the input signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) can approach that of the input signal level. When

a large number of samples are averaged a very precise value of the analog signal is

obtained. This averaging is carried out in the DSP section which implements decimation,

integration and DC offset cancellation of the supplied

∑∆ signals. The gain of the decimation

filters is 1.004 for the voltage channel and 0.502 for the current channel. The resulting signal

has a resolution of 11bits for voltage channel and 16 bits for current channel.

8.4

Zero crossing detection

The STPM01 has a zero crossing detector circuit on the voltage channel which can be used

by application for synchronization of some utility equipment to event of zero crossing of line

voltage. This circuit produces the internal signal ZCR which has a rising edge every time the

line voltage crosses zero and a negative edge every time the voltage reaches its positive or

negative peak. The ZCR signal is then at twice the line voltage frequency. The ZCR signal is

available on the MOP pin only when STPM01 works as peripheral with the configuration bit

APL=0.

Figure 14.

First order

∑∆ A/D Converter

DAC

Integrator

fCLK/4

Input analog signal

Output digital signal

∫

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