 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
SPSB100 데이터시트(PDF) 72 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPSB100 데이터시트(HTML) 72 Page - STMicroelectronics |
|
|
72 / 214 page  7.6 LDO2 voltage regulator The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6 V ≤ VFBB ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. The same parameter values in both 5 V and 3.3 V conditions applies unless otherwise specified. Table 27. LDO2 Symbol Parameter Condition Min Typ Max Unit VLDO2_5 Output voltage VS ≥ 6.0 V 4.9 5.0 5.15 V VLDO2_33 Output voltage VS ≥ 6.0 V 3.23 3.3 3.399 V VLDO2_ACC_25(1) Output voltage tracking accuracy ILOAD = 100 μA to 5 mA VFBB = 8 V to 18 V Tj = 25 °C -10 - 10 mV VLDO2_ACC_130 Output voltage tracking accuracy ILOAD = 100 μA to 5 mA VFBB = 8 V to 18 V Tj = 130 °C -20 - 20 mV VLDO2_OV Overvoltage threshold for LDO2 105 108.5 112 % tLDO2_OV(2) LDO2 overvoltage filter time 12 15 22 μs VLDO2_PG Power-good voltage threshold for LDO2 91.5 95 98.5 % VLDO2_UV Undervoltage threshold for LDO2 88 91.5 95 % tLDOLDO2_UV(2) LDO2 undervoltage filter time 12 15 22 μs tLDO2_PG_TO(2) LDO2 timeout for power-good 4.8 6 7.5 ms VLDO2_DP Drop-out voltage ILOAD = 10 mA - 0.5 1.0 V ILDO2_CCmax Short circuit output current (to GND) Current limitation 15 30 45 mA CLDO2(3) Load capacitor1 Ceramic (± 20%) 1 - 10 µF 1. Guarantee by design. 2. Digital implementation is guaranteed by scan test. 3. Nominal capacitor value required for stability of the regulator. Tested with 1 µF ceramic (±20%). The capacitor must be located close to the regulator output pin. A 2.2 μF capacitor value is recommended to minimize the DPI (Direct power injection) stress in the application. 7.7 Boost controller The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 3 V ≤ VS ≤ 29 V, Tj = -40 °C to 150 °C, unless otherwise specified. Table 28. Boost controller Symbol Parameter Condition Min Typ Max Unit VFBB_UV_R BOOST rising enable threshold Input voltage required on initial start-up to enable the boost 5.0 5.25 5.5 V VFBB_UV_F BOOST falling disable threshold Power down threshold 4.65 4.9 5.15 V VFBB_UV_HYS Boost enable hysteresis 0.2 0.35 0.5 V TF_FBB_UV(1) digital filter time on FBB POR 12 15 22 µs VFBB_REG1 VFBB regulation threshold If BUCK1 and BUCK2 voltage settings are = 3.3 V 7.7 8.0 8.3 V VFBB_REG2 VFBB regulation threshold If BUCK1 or BUCK2 voltage settings are above 3.3 V (5.0 or 6.5 V) 9.2 9.5 9.8 V SPSB100 Electrical characteristics DS14640 - Rev 1 page 72/214 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
