VD66GY datasheet(30/37 Pages) STMICROELECTRONICS

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8.7

I²C interface - SDA, SCL

Table 16. I²C timing

The values below are for all process, voltage, and temperature conditions.

Parameter

Symbol

Fast mode

Fast mode plus

Unit

Min.

Max.

Min.

Max.

SCL clock frequency

tSCL

400

1000 kHz

Hold time (repeated) START condition. After this period,

the first clock pulse is generated

tHD.STA

0.6

—

0.26

—

µs

LOW period of the SCL clock

tLOW

1.3

—

0.5

—

HIGH period of the SCL clock

tHIGH

0.6

—

0.26

—

Setup time for a repeated START condition

tSU.STA

0.6

—

0.26

—

Data hold time

tHD.DAT

—

Data set-up time

tSU.DAT

100

—

Rise time of both SDA and SCL

300

—

120

Fall time of both SDA and SCL

20 x (VDD /

5.5V)

300 15 x (VDD / 5.5V) 120

Set-up time for STOP condition

tSU.STO

0.6

—

0.26

—

µs

Bus free time between a STOP and START condition

tBUF

1.3

—

0.5

—

Capacity load for each bus line

—

400

—

550

Data valid time

tVD.DAT

—

0.9

—

0.45

µs

Data valid acknowledge time

tVD.ACK

—

0.9

—

0.45

Noise margin at LOW level for each connected device

(including hysteresis)

VnL

0.054 x VDD

—

0.054 x VDD

—

Noise margin at HIGH level for each connected device

(including hysteresis)

VnH

—

Figure 20. I²C timing

VD66GY

Electrical characteristics

DS13838 - Rev 7

page 30/37

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