TC7129 datasheet(16/28 Pages) MICROCHIP

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TC7129

DS21459D-page 16

Figure 4-15:

Digital Ground (DGND) and

Common Outputs.

4.14

Low Battery

The low battery annunciator turns on when supply volt-

age between V– and V+ drops below 6.8V. The internal

zener diode has a threshold of 6.3V. When the supply

voltage drops below 6.8V, the transistor tied to V– turns

off pulling the “Low Battery” point high.

4.15

Sequence and Results Counter

A sequence counter and associated control logic pro-

vide signals that operate the analog switches in the

integrator section. The comparator output from the inte-

grator gates the results counter. The results counter is

a six-section up/down decade counter that holds the

intermediate results from each successive integration.

4.16

Overrange and Underrange

Outputs

When the results counter holds a value greater than

±19,999, the DP4/OR output (Pin 20) is driven high.

When the results counter value is less than ±1000, the

DP3/UR output (Pin 21) is driven high. Both signals are

valid on the falling edge of LATCH/HOLD (L/H) and do

not change until the end of the next conversion cycle.

The signals are updated at the end of each conversion,

unless the L/H input (Pin 22) is held high. Pins 20 and

21 can also be used as inputs for external control of

decimal points 3 and 4. Figure 4-14 shows a schematic

of the input/output nature of these pins.

4.17

LATCH/Hold

The L/H output goes low during the last 100 cycles of

each conversion. This pulse latches the conversion

data into the display driver section of the TC7129. This

pin can also be used as an input. When driven high, the

display will not be updated; the previous reading is

displayed. When driven low, the display reading is not

latched;

the

sequence

counter

reading

will

displayed. Since the counter is counting much faster

than the backplanes are being updated, the reading

shown in this mode is somewhat erratic.

4.18

Display Driver

The TC7129 drives a triplexed LCD with three back-

planes. The LCD can include decimal points, polarity

sign and annunciators for continuity and low battery.

Figure 4-16 shows the assignment of the display

segments to the backplanes and segment drive lines.

The backplane drive frequency is obtained by dividing

the oscillator frequency by 1200. This results in a back-

plane drive frequency of 100 Hz for 60 Hz operation

(120 kHz crystal) and 83.3 Hz for 50 Hz operation

(100 kHz crystal).

Backplane waveforms are shown in Figure 4-17.

These appear on outputs BP1, BP2, BP3 (pins 16, 17

and 18). They remain the same, regardless of the

segments being driven.

Other display output lines (pins 4 through 15) have

waveforms that vary depending on the displayed

values. Figure 4-18 shows a set of waveforms for the

A, G, D outputs (pins 5, 8, 11 and 14) for several

combinations of “ON” segments.

The ANNUNCIATOR DRIVE output (pin 3) is a square

wave, running at the backplane frequency (100 Hz or

83.3 Hz) with a peak-to-peak voltage equal to DGND

voltage. Connecting an annunciator to pin 3 turns it on;

connecting it to its backplane turns it off.

–

12 µA

TC7129

Logic

Section

3.2V

V+

V–

COM

DGND

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