TC7135CPL datasheet(6/24 Pages) MICROCHIP

6 / 24 page

TC7135

DS21460C-page 6

 2004 Microchip Technology Inc.

3.0

DETAILED DESCRIPTION

All pin designations refer to the 28-pin PDIP package.

3.1

Dual-Slope Conversion Principles

The TC7135 is a dual-slope, integrating A/D converter.

understanding

the

dual-slope

conversion

technique will aid in following the detailed TC7135

operational theory.

The conventional dual-slope converter measurement

cycle has two distinct phases:

Input signal integration.

Reference voltage integration (de-integration).

The input signal being converted is integrated for a

fixed time period. Time is measured by counting clock

pulses. An opposite polarity constant reference voltage

is then integrated until the integrator output voltage

returns to zero. The reference integration time is

directly proportional to the input signal.

simple

dual-slope

converter,

complete

conversion requires the integrator output to “ramp-up”

and “ramp-down”.

A simple mathematical equation relates the input

signal, reference voltage and integration time:

EQUATION 3-1:

For a constant VIN:

EQUATION 3-2:

The dual-slope converter accuracy is unrelated to the

integrating resistor and capacitor values, as long as

they are stable during a measurement cycle. An

inherent benefit is noise immunity. Noise spikes are

integrated, or averaged, to zero during the integration

periods.

Integrated ADCs are immune to the large conversion

errors that plague successive approximation converters

in high-noise environments (see Figure 3-1).

FIGURE 3-1:

Basic Dual-Slope Converter.

3.2

TC7135 Operational Theory

The TC7135 incorporates a system zero phase and

integrator output voltage zero phase to the normal two-

phase

dual-slope

measurement

cycle.

Reduced

system errors, fewer calibration steps and a shorter

overrange recovery time result.

The TC7135 measurement cycle contains four phases:

System zero.

Analog input signal integration.

Reference voltage integration.

Integrator output zero.

Internal analog gate status for each phase is shown in

Figure 3-1.

TABLE 3-1:

INTERNAL ANALOG GATE STATUS

INTCINT

------------------------

IN T

()DT

INT

∫

REFTDEINT

INTCINT

--------------------------------

Where:

VREF = Reference voltage

TINT = Signal integration time (fixed)

TDEINT = Reference voltage integration time

(variable)

REFTDEINT

IN T

--------------------------------

REF

Voltage

Analog Input

Signal

Display

Switch

Drive

Control

Logic

Clock

Counter

Polarity Control

Phase

Control

VIN

≈ V

REF

Variable

Reference

Integrate

Time

Fixed

Signal

Integrate

Time

Integrator

Comparator

VIN

≈ 1/2 V

REF

Conversion Cycle Phase

SWI

SWRI+SWRI-SWZ

SWR

SW1

SWIZ

Reference Figures

System Zero

—

Closed

—

Figure 3-2

Input Signal Integration

Closed

—

Figure 3-3

Reference Voltage Integration

—

Closed*

—

Closed

—

Figure 3-4

Integrator Output Zero

—

Closed

Figure 3-5

* Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.

TC7135CPL 데이터시트(PDF) 6 Page - Microchip Technology

TC7135CPL 데이터시트(HTML) 6 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

데이터시트 다운로드

링크 URL