Data Sheet

AD9914

REGISTER MAP AND BIT DESCRIPTIONS

analog.com

Rev. G | 41 of 48

Table 15. Register Map

Register Name

(Serial Address)

Bit Range

(Parallel

Address)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)1

USR0 (0x1B)

[7:0] (0x6C)

Requires register default value settings (0x00)

0x00

[15:8]

(0x6D)

Requires register default value settings (0x08)

0x08

[23:16]

(0x6E)

Requires register default value settings (0x00)

0x00

[31:24]

(0x6F)

Open

PLL lock

Read only

1 A master reset is required after power up. The master reset returns the internal registers to the default values.

2 The DAC CAL enable bit must be manually set and then cleared after each power-up and every time REF CLK or the internal system clock is changed. This initiates an

internal calibration routine to optimize the setup and hold times for internal DAC timing. Failure to calibrate degrades ac performance or makes the device nonfunctional.

REGISTER BIT DESCRIPTIONS

The serial input/output port registers span an address range of 0 to

27 (0x00 to 0x1B in hexadecimal notation). This represents a total

of 28 individual serial registers. If programming in parallel mode,

the number of parallel registers increases to 112 individual parallel

registers. Additionally, the registers are assigned names according

to the functionality. In some cases, a register is given a mnemonic

descriptor. For example, the register at Serial Address 0x00 is

named Control Function Register 1 and is assigned the mnemonic

CFR1.

This section provides a detailed description of each bit in the

AD9914 register map. For cases in which a group of bits serves a

specific function, the entire group is considered a binary word and

is described in aggregate.

This section is organized in sequential order of the serial addresses

of the registers. Each subheading includes the register name and

optional register mnemonic (in parentheses). Also given is the serial

address in hexadecimal format and the number of bytes assigned

to the register.

Following each subheading is a table containing the individual bit

descriptions for that particular register. The location of the bit(s) in

the register is indicated by a single number or a pair of numbers

separated by a colon; that is, a pair of numbers (A:B) indicates a

range of bits from the most significant (A) to the least significant (B).

For example, [5:2] implies Bit Position 5 to Bit Position 2, inclusive,

with Bit 0 identifying the LSB of the register.

Unless otherwise stated, programmed bits are not transferred to the

internal destinations until the assertion of the I/O_UPDATE pin or a

profile pin change.