Data Sheet

AD9915

REGISTER MAP AND BIT DESCRIPTIONS

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Rev. G | 48 of 51

Table 21. Bit Descriptions for DAC

Bit(s)

Mnemonic

Description

26

Auxiliary divider power-down

0 = enables the SYNC OUT circuitry.

1 = disables the SYNC OUT circuitry

25

DAC CAL clock power-down

0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0.

1 = disables the DAC CAL clock.

24

DAC CAL enable

1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and any time the internal

system clock is changed.

[23:0]

(See description)

These bits must always be programmed with the default values listed in the default column in Table 17.

Digital Ramp Lower Limit Register—Address 0x04

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 22. Bit Descriptions for Digital Ramp Lower Limit Register

Bit(s)

Mnemonic

Description

[31:0]

Digital ramp lower limit

32-bit digital ramp lower limit value.

Digital Ramp Upper Limit Register—Address 0x05

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 23. Bit Descriptions for Digital Ramp Limit Register

Bit(s)

Mnemonic

Description

[31:0]

Digital ramp upper limit

32-bit digital ramp upper limit value.

Rising Digital Ramp Step Size Register—Address 0x06

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 24. Bit Descriptions for Rising Digital Ramp Step Size Register

Bit(s)

Mnemonic

Description

[31:0]

Rising digital ramp increment step

size

32-bit digital ramp increment step size value.

Falling Digital Ramp Step Size Register—Address 0x07

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.

Table 25. Bit Descriptions for Falling Digital Ramp Step Size Register

Bit(s)

Mnemonic

Description

[31:0]

Falling digital ramp decrement step

size

32-bit digital ramp decrement step size value.

Digital Ramp Rate Register—Address 0x08

This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section

for details.