MCP3301-CISLASHMS datasheet(17/32 Pages) MICROCHIP

17 / 32 page

DS21700C-page 17

MCP3301

FIGURE 6-3:

Analog Input Model.

6.2.1

MAINTAINING MINIMUM CLOCK

SPEED

When the MCP3301 initiates, charge is stored on the

sample capacitor. When the sample period is complete,

the device converts one bit for each clock that is

received. It is important for the user to note that a slow

clock rate will allow charge to bleed off the sample

capacitor while the conversion is taking place. For the

MCP330X devices, the recommended minimum clock

speed during the conversion cycle (tCONV) is 85 kHz.

Failure to meet this criteria may introduce linearity

errors into the conversion outside the rated specifica-

tions. It should be noted that, during the entire conver-

sion

cycle,

the

A/D

converter

does

not

have

requirements for clock speed or duty cycle as long as

all timing specifications are met.

6.3

Biasing Solutions

For pseudo-differential bipolar operation, the biasing

circuit shown in Figure 6-4 shows a single-ended input

AC coupled to the converter. This configuration will give

a digital output range of -4096 to +4095. With the 2.5V

reference, the LSB size is equal to 610 µV.

Although the ADC is not production tested with a 2.5V

reference as shown, linearity will not change more than

0.1 LSB. See Figure 2-2 and 2-9 for DNL and INL

errors versus V

REF

at V

DD = 5V. A trade-off exists

between the high pass corner and the acquisition time.

The value of C will need to be quite large in order to

bring down the high pass corner. The value of R needs

to be 1 k

Ω or less, since higher input impedances

require additional acquisition time. Using the values in

Figure 6-4, we have a 100 Hz corner frequency. See

Figure 2-12 for the relationship between input imped-

ance and acquisition time.

FIGURE 6-4:

Pseudo-differential biasing

circuit for bipolar operation.

Using an external operational amplifier on the input

allows for gain and buffers the input signal from the

input to the ADC, allowing for a higher source

impedance. This circuit is shown in Figure 6-5.

CHx

7pF

T = 0.6V

LEAKAGE

Sampling

Switch

S = 1 kΩ

SAMPLE

= DAC capacitance

= 25 pF

±1 nA

Legend

signal source

Rss

source impedance

CHx

input channel pad

Cpin = input pin capacitance

threshold voltage

Ileakage

leakage current at the pin

due to various junctions

sampling switch

sampling switch resistor

Csample

sample/hold capacitance

VDD = 5V

0.1 µF

IN+

IN-

VREF

MCP3301

1µF

MCP1525

VIN

VOUT

0.1 µF

10 µF C

VIN

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