M68HC08 datasheet(98/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

System Integration Module (SIM)

Freescale Semiconductor

7.6.1 Interrupts

An interrupt temporarily changes the sequence of program execution to

respond to a particular event. Figure 7-9 flow charts the handling of

system interrupts.

Interrupts are latched, and arbitration is performed in the SIM at the start

of interrupt processing. The arbitration result is a constant that the CPU

uses to determine which vector to fetch. Once an interrupt is latched by

the SIM, no other interrupt can take precedence, regardless of priority,

until the latched interrupt is serviced (or the I bit is cleared).

At the beginning of an interrupt, the CPU saves the CPU register

contents on the stack and sets the interrupt mask (I bit) to prevent

additional interrupts. At the end of an interrupt, the RTI instruction

recovers the CPU register contents from the stack so that normal

processing can resume. Figure 7-7 shows interrupt entry timing. Figure

7-8 shows interrupt recovery timing.

Figure 7-7

. Interrupt Entry

Figure 7-8. Interrupt Recovery

MODULE

IDB

R/W

INTERRUPT

DUMMY

SP – 1

SP – 2

SP – 3

SP – 4

VECT H

VECT L

START ADDR

IAB

DUMMY

PC – 1[7:0] PC – 1[15:8]

CCR

V DATA H

V DATA L

OPCODE

I BIT

MODULE

IDB

R/W

INTERRUPT

SP – 4

SP – 3

SP – 2

SP – 1

PC + 1

IAB

CCR

PC – 1[7:0] PC – 1[15:8] OPCODE

OPERAND

I BIT

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