MCP98242-BESLASHST datasheet(8/46 Pages) MICROCHIP

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MCP98242

DS21996A-page 8

4.0

SERIAL COMMUNICATION

4.1

2-Wire SMBus/Standard Mode

I2C™ Protocol-Compatible

Interface

The MCP98242 serial clock input (SCLK) and the

bidirectional serial data line (SDA) form a 2-wire

bidirectional SMBus/Standard mode I2C compatible

communication port (refer to the Input/Output Pin DC

Characteristics Table and Sensor And EEPROM Serial

Interface Timing Specifications Table).

The following bus protocol has been defined:

TABLE 4-1:

MCP98242 SERIAL BUS

PROTOCOL DESCRIPTIONS

4.1.1

DATA TRANSFER

Data transfers are initiated by a Start condition

(START), followed by a 7-bit device address and a

read/write bit. An Acknowledge (ACK) from the slave

confirms the reception of each byte. Each access must

be terminated by a Stop condition (STOP).

Repeated communication is initiated after tB-FREE.

This device does not support sequential register

read/write. Each register needs to be addressed using

the Register Pointer.

This device supports the Receive Protocol. The

read. Each repeated read or receive begins with a Start

condition and address byte. The MCP98242 retains the

previously selected register. Therefore, it outputs data

from the previously-specified register (repeated pointer

specification is not necessary).

4.1.2

MASTER/SLAVE

The bus is controlled by a master device (typically a

microcontroller) that controls the bus access and

generates the Start and Stop conditions. The

MCP98242 is a slave device and does not control other

devices in the bus. Both master and slave devices can

operate as either transmitter or receiver. However, the

master device determines which mode is activated.

4.1.3

START/STOP CONDITION

A high-to-low transition of the SDA line (while SCLK is

high) is the Start condition. All data transfers must be

preceded by a Start condition from the master. If a Start

condition is generated during data transfer, the

MCP98242 resets and accepts the new Start condition.

A low-to-high transition of the SDA line (while SCLK is

high) signifies a Stop condition. If a Stop condition is

introduced during data transmission, the MCP98242

releases the bus. All data transfers are ended by a Stop

condition from the master.

4.1.4

ADDRESS BYTE

Following the Start condition, the host must transmit an

8-bit address byte to the MCP98242. The address for

the

MCP98242

Temperature

Sensor

‘0011,A2,A1,A0’ in binary, where the A2, A1 and A0

bits are set externally by connecting the corresponding

pins to VDD ‘1’ or GND ‘0’. The 7-bit address transmit-

ted in the serial bit stream must match the selected

address for the MCP98242 to respond with an ACK. Bit

8 in the address byte is a read/write bit. Setting this bit

to ‘1’ commands a read operation, while ‘0’ commands

a write operation (see Figure 4-1).

Term

Description

Master

The device that controls the serial bus,

typically a microcontroller.

Slave

The device addressed by the master,

such as the MCP98242.

Transmitter Device sending data to the bus.

Receiver

Device receiving data from the bus.

START

A unique signal from master to initiate

serial interface with a slave.

STOP

A unique signal from the master to

terminate serial interface from a slave.

Read/Write A read or write to the MCP98242

registers.

ACK

A receiver Acknowledges (ACK) the

reception of each byte by polling the

bus.

NAK

A receiver Not-Acknowledges (NAK) or

releases the bus to show End-of-Data

(EOD).

Busy

Communication is not possible

because the bus is in use.

Not Busy

The bus is in the idle state, both SDA

and SCLK remain high.

Data Valid

SDA must remain stable before SCLK

becomes high in order for a data bit to

be considered valid. During normal

data transfers, SDA only changes state

while SCLK is low.

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