TDA8707 datasheet(8/16 Pages) PHILIPS

8 / 16 page

1996 Feb 01

Philips Semiconductors

Product speciﬁcation

Triple RGB 6-bit video analog-to-digital

interface

TDA8707

Notes to the characteristics

1. VDDA and VDDD should be supplied from the same power supply and decoupled separately.

2. The analog supply current is directly proportional to the series resistance between VDDA and CLREF.

3. CREFH and CREFL are connected respectively to the top and bottom reference ladders of the 3 analog-to-digital

converters.

4. VI(p-p) =(VREFL − VREFH)/buffer gain factor. See Table for gain factor selection. When clamping at code 0 is used,

active video signal amplitude VACT should be:

5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a

digital-to-analog converter.

6. VI(p-p) = ∆REF with fi = 4.43 MHz.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

8. Output data acquisition: output data is available after the maximum delay time of td.

Table 1

Typical output coding (VREFH =2V; VREFL = 0.5 V referenced to VSSA, SLT = logic 0; buffer ratio = 1.5;

Tamb =25°C)

Table 2

Mode selection

STEP

VI(p-p)

BINARY OUTPUT BITS

−

<0.333 =

000000

0.349

0.364

1.317

1.333

−

>1.333 =

111111

SLT

BUFFER RATIO

TYPICAL VI(p-p) FULL SCALE

1.5

2.0

ACT

REFH

REFL

–

()

buffer gain factor

-----------------------------------------------

REFL

1.5

----------------

REFH

1.5

-----------------

REFH

REFL

–

1.5

----------------------------------------

REFH

REFL

–

2.0

----------------------------------------

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