TDA8752 datasheet(13/36 Pages) PHILIPS

13 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

The COAST pin is used to disconnect the PLL phase

frequency detector during the frame flyback or the

unavailability of the CKREF signal. This signal can

normally be derived from the VSYNC signal.

The clock output is able to drive an external 10 pF load

(for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling

frequency of up to 100 MHz for the TDA8752/8 and up

to 60 MHz for the TDA8752/6.

2. When an RGB signal is at a pixel frequency exceeding

100 to 200 MHz, it is possible to follow one of the two

possibilities given below;

a) Using one TDA8752; the sampling rate can be

reduced by a factor of two, by sampling the even

pixels in the even frame and the odd pixels in the

odd frame. The INV pin is used to toggle between

frames.

b) Using two TDA8752s the PLL of the master

TDA8752 is used to drive both ADC clocks.

The PLL of the slave TDA8752 is disconnected and

the CKBO of the master TDA8752 is connected to

pin CKEXT of both TDA8752.

The master TDA8752 is used to sample the even

pixels and the slave TDA8752 for odd pixels, using

a 180

° phase shift between the clocks (CKADCO

pins). The master chip has its INV pin LOW while

the slave chip has its INV pin HIGH, which

guarantees the 180

° shift ADC clock drive. It is then

necessary to adjust phase B of the master chip.

Special care should be taken with the quality of the

input signal (input setting time).

If CKREFO output signal at the master chip is

needed, it is possible to use one of the two phase A

values in order to avoid set-up and hold problems

in the SYNCHRO function; e.g.

PHASEA = 100000 and PHASEA = 111111.

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