1999 Mar 09

20

Philips Semiconductors

Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

Table 8

Phase registers bits

The default programmed value is as follows:

• No external clock: CKA at logic 0

• No use of the second clock: CKB at logic 0

• Phase shift for CKAO and CKADCO = 0°

• Phase shift for CKBO = 0°.

Table 9

Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752s can be used on the same

are available, see Tables 10 and 11.

Table 10 Address sequence for mode 0

Where: S = START condition, ACK = acknowledge and P = STOP condition.

Table 11 Address sequence for mode 1

Where: S = START condition, ACK = acknowledge and P = STOP condition.

Pa4, Pb4

Pa3, Pb3

Pa2, Pb2

Pa1, Pb1

Pa0, Pb0

PHASE SHIFT (

°)

000000

00001

11.25

↓↓↓↓↓↓

↓↓↓↓↓↓

11110

337.5

11111

348.75

A7

A6

A5

A4

A3

A2

A1

A0

10011

ADD2

ADD1

0

S

IC ADDRESS

ACK

SUBADDRESS

REGISTER1

ACK

DATA

REGISTER1

(see Table 1)

ACK

SUBADDRESS

REGISTER2

ACK

....

P

S

IC ADDRESS

ACK

SUBADDRESS

xxx1 1111

ACK

DATA

REGISTER1

(see Table 1)

ACK

DATA

REGISTER2

ACK

....

P