SLIC Products

11

12. Tested with 0

Ω source impedance. 2 MΩ is specified for system design purposes only.

the group delay to less than 2

µs. The effect of group delay on linecard performance may be compensated for by using

QSLAC™ or DSLAC™ devices.

Note:

*

A logic Low on E0 disables the DET output into the Open Collector state.

Table 1.

SLIC Decoding

DET Output

State

C3 C2 C1

Two-Wire Status

E0 = 1*

E1 = 0

E0 = 1*

E1 = 1

0

0

0

0

Open Circuit

Ring trip

Ring trip

1

0

0

1

Ringing

Ring trip

Ring trip

2

0

1

0

Active

Loop detector

Ground key

3

0

1

1

On-hook TX (OHT)

Loop detector

Ground key

4

1

0

0

Tip Open

Loop detector

—

5

1

0

1

Reserved

Loop detector

—

6

1

1

0

Active Polarity Reversal

Loop detector

Ground key

7

1

1

1

OHT Polarity Reversal

Loop detector

Ground key

Table 2.

User-Programmable Components

amplifier pole and any external stray capacitance between

VTX and RSN must be taken into account.

VTX

RSN

300 k

Ω

300 k

Ω

30 pF

Z

T

1000 Z

2WIN

2R

F

–

()

=

Z

RX

Z

L

G

42L

-----------

1000

Z

T

•

Z

T

1000 Z

L

2R

F

+

()

+

----------------------------------------------------

•

=

R

DC 1

R

DC2

50 R

FEED

2R

F

–

()

=

+

C

DC

1.5 ms

R

DC1

R

DC 2

+

R

DC 1

R

DC2

•

--------------------------------

•

=

R

D

365

I

T

---------

C

D

0.5 ms

R

D

------------------

=

,

=