July 1994

8

Philips Semiconductors

Preliminary specification

Programmable deflection controller

TDA9151B

Table 3 Explanation of control bits shown in Table 2.

Table 4 Clock frequency control bit (pin 5; note 1).

Note

1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground

very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in

Table 5.

Table 5 Line duration with prescaler.

Note

1. Combination not allowed.

CONTROL BITS

DESCRIPTION

LFSS

line frame start/stop

DINT

de-interlace

BLDS

bleeder mode selection

GBS

guard band selection

VAP

FBL

flyback slicing level

WS

wait state on/off

MS

mode select

CSU

clamping suppression mode

PRD

protection/detection mode

DIP

de-interlace phase

CPR

compression on/off

VPR

vertical power reduction mode

CONTROL BIT

LOGIC

FUNCTION

LLCS

0

1

LLC (MHz)

ON (

µs)

OFF (

µs)

6.75

note 1

64

13.5

64

32

27

32

note 1