ADA4945-1ACPZ-R2 datasheet(52/57 Pages) AD

52 / 57 page

Data Sheet

ADA4945-1

analog.com

Rev. A

52 of 57

Figure 111. Series Resistance vs. Load Capacitance

Figure 112. Series Resistance with a Capacitive Load Test Circuit

Output Clamps

The ADA4945-1 implements output voltage clamps to effectively limit the differential and common-mode signal

levels, thereby protecting circuitry following the ADA4945-1 from being overdriven. The operation of these clamps is

discussed in the Theory of Operation section. Figure 113 shows an example where the output voltage clamp may be

used while driving an ADC. In this example, the ADA4945-1 is operating from +7 V and −2 V supplies, and the ADC is

using +5 V reference. In such a scenario, the ADC input can potentially be overdriven if no clamping were present. By

connecting the clamps to the positive and negative references of the ADC, the differential and common-mode signal

levels are limited as shown in Figure 114 and Figure 115. Note that the differential signals are clamped ~500 mV

beyond the clamp set voltage to allow full swing to the references. The common-mode signal is clamped right at the

clamp set voltages.

Figure 113. ADA4945-1 Output Voltage Clamp Usage

100

1000

LOAD CAPACITANCE (pF)

FULL POWER MODE

LOW POWER MODE

+IN

–OUT

+OUT

–FB

+FB

–IN

VOCM

0.1µF

+5V

–5V

VIN

ADA4945-1

+7V

–2V

+2.5V

ADC

–IN

+IN

VREF

REF

+VCLAMP

+5V

–VCLAMP

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