R2J20701NP

REJ03G1459-0300 Rev.3.00 Jun 20, 2007

Page 21 of 27

Timing Chart

Peak Current Control

(EO-Vbe) / 2

(Internal signal)

EO

RAMP

TLD

50 ns (typ.)

Max. Duty

(Internal signal)

RES

(Internal signal)

50 ns (typ.)

0 V

VIN

SW

0 V

The high-side MOS FET is turned

off by the max. duty signal.

To obtain stable operation, settings should be such that the level on the switching node is

high for at least 80 ns.

Note:

Propagation delay is ignored.