PIC18F44J10-ESLASHML datasheet(265/358 Pages) MICROCHIP

265 / 358 page

Preliminary

DS39682C-page 263

PIC18F45J10 FAMILY

INCFSZ

Increment f, Skip if 0

Syntax:

INCFSZ

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) + 1

→ dest,

skip if result = 0

Status Affected:

None

Encoding:

0011

11da

ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

INCFSZ

CNT, 1, 0

NZERO

ZERO

Before Instruction

Address (HERE)

After Instruction

CNT

CNT + 1

If CNT

Address (ZERO)

If CNT

≠

Address (NZERO)

INFSNZ

Increment f, Skip if not 0

Syntax:

INFSNZ

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) + 1

→ dest,

skip if result

≠ 0

Status Affected:

None

Encoding:

0100

10da

ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

INFSNZ

REG, 1, 0

ZERO

NZERO

Before Instruction

Address (HERE)

After Instruction

REG

REG + 1

If REG

≠

Address (NZERO)

If REG

Address (ZERO)

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