PIC18F44J10-ESLASHML datasheet(31/358 Pages) MICROCHIP

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Preliminary

DS39682C-page 29

PIC18F45J10 FAMILY

2.8

Power-up Delays

Power-up delays are controlled by two timers, so that

no external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply is stable under nor-

mal circumstances and the primary clock is operating

and stable. For additional information on power-up

delays, see Section 4.5 “Power-up Timer (PWRT)”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 23-10). It is always enabled.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crystal oscillator is stable (HS modes). The OST does

this by counting 1024 oscillator cycles before allowing

the oscillator to clock the device.

There is a delay of interval TCSD (parameter 38,

Table 23-10), following POR, while the controller

becomes ready to execute instructions.

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode

OSC1 Pin

OSC2 Pin

EC, ECPLL

Floating, pulled by external clock

At logic low (clock/4 output)

HS, HSPLL

Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

Note:

See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

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