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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC18F44J10-E/ML 데이터시트(PDF) 327 Page - Microchip Technology |
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PIC18F44J10-E/ML 데이터시트(HTML) 327 Page - Microchip Technology |
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327 / 358 page  © 2007 Microchip Technology Inc. Preliminary DS39682C-page 325 PIC18F45J10 FAMILY FIGURE 23-18: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 23-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 23-19: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 23-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS 121 121 120 122 TX/CK RX/DT pin pin Note: Refer to Figure 23-3 for load conditions. Param No. Symbol Characteristic Min Max Units Conditions 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns 125 126 TX/CK RX/DT pin pin Note: Refer to Figure 23-3 for load conditions. Param. No. Symbol Characteristic Min Max Units Conditions 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns |
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