PIC18F44J10-ESLASHML datasheet(110/358 Pages) MICROCHIP

110 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 108

Preliminary

TABLE 9-11:

PORTE I/O SUMMARY

TABLE 9-12:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Function

TRIS

Setting

I/O

Type

Description

RE0/RD/AN5

RE0

DIG

LATE<0> data output; not affected by analog input.

PORTE<0> data input; disabled when analog input enabled.

TTL

PSP read enable input (PSP enabled).

AN5

ANA

A/D input channel 5; default input configuration on POR.

RE1/WR/AN6

RE1

DIG

LATE<1> data output; not affected by analog input.

PORTE<1> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN6

ANA

A/D input channel 6; default input configuration on POR.

RE2/CS/AN7

RE2

DIG

LATE<2> data output; not affected by analog input.

PORTE<2> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN7

ANA

A/D input channel 7; default input configuration on POR.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTE(1)

—

RE2

RE1

RE0

LATE(1)

—

PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE(1)

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1:

These registers are not available in 28-pin devices.

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