PIC12F615 datasheet(21/168 Pages) MICROCHIP

21 / 168 page

Preliminary

DS41302A-page 19

PIC12F609/615/12HV609/615

2.2.2.5

PIR1 Register

The PIR1 register contains the Peripheral Interrupt flag

bits, as shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

—ADIF(1)

CCP1IF(1)

—CMIF

—TMR2IF(1)

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIF: A/D Interrupt Flag bit(1)

= A/D conversion complete

= A/D conversion has not completed or has not been started

bit 5

CCP1IF: CCP1 Interrupt Flag bit(1)

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4

Unimplemented: Read as ‘0’

bit 3

CMIF: Comparator Interrupt Flag bit

= Comparator output has changed (must be cleared in software)

= Comparator output has not changed

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1)

= Timer2 to PR2 match occurred (must be cleared in software)

= Timer2 to PR2 match has not occurred

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

= Timer1 register overflowed (must be cleared in software)

= Timer1 has not overflowed

Note 1: PIC12F615/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.

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