ST25R100 datasheet(13/86 Pages) STMICROELECTRONICS

13 / 86 page

5.3

Supply system

The ST25R100 features two positive supply pins:

•

VDD_IO is used to define the supply level for digital communication pins (MISO, MOSI, SCLK, BSS, and

IRQ). Digital communication pins interface with ST25R100 logic through level shifters, therefore the internal

supply voltage can be either higher or lower than VDD_IO.

•

VDD is the main power supply pin. It supplies the ST25R100 blocks through the following:

–

Regulator VDD_D

–

Regulator VDD_A

–

Regulator VDD_DR

–

Regulator VDD_AM

The recommended blocking capacitors for supply pins are as following:

•

2.2 μF in parallel with 10 nF for: VDD, VDD_DR, VDD_D, and VDD_AM (pin 5, 6, 7, and 8)

•

1 μF in parallel with 10 nF for AGD and VDD_IO (pin 3 and 15)

Figure 7. Supply system

VDD

VDD_D

VDD_A

REG

AUTOREG

BGR

VDD_D

REG

AGD

Buff

VDD_AM

VDD_DR

VDD_A

AGDC

VDD_D

VDD_A1

VDD_DR

REG

VDD_AM

REG

POR

Note:

•

BGR: Bandgap reference

•

AUTOREG: Automatic regulator adjustment

ST25R100

Application information

DS14139 - Rev 5

page 13/86

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