7.2.2

Power-on and power-off sequences, and power supply glitch tolerance

The power-on sequence on STSAFE-A120 products must follow the requirements mentioned below:

•

The RESET pin must not be tight to high prior to the VCC power pin.

•

The RESET pin must be tied to low prior to or simultaneously with the VCC power pin.

•

The voltage applied to the VCC pin must be less than or equal to 0.3 V prior to starting a new power-on

sequence.

For more information, refer to Figure 17. Power-on and reset sequence.

For security purposes, the STSAFE-A120 embeds detectors. When these are triggered, the STSAFE-A120

device enters the reset state until a power cycle or a reset event occurs.

It is recommended to use an application that is able to manage the RESET pin through a host GPIO to force reset

upon alarm detection.

7.2.3

Reset pin (external reset)

The circuit is in reset state when the reset signal available on the RESET pin is at logical level ‘0’. If this signal is

low for less than tWL, it is not taken into account.

When the RESET pin is floating, an external reset is not available and the device remains in a reset state as the

pin is connected to an internal weak pull-down.

When pin VCC is tied high, if the RESET pin switches from high to low and then to high again, a warm reset

occurs. For more information, refer to Figure 18. Warm reset sequence.

7.2.4

Power-on and reset sequence

Figure 17. Power-on and reset sequence

I2C bus

VCC

90%

10%

SVCC

tVCC

RESET

90%

10%

tHL

tR

tI2C_READY

NACK on I2C bus

ACK on I2C bus

Figure 18. Warm reset sequence

ACK on I2C bus

RESET

90%

10%

90%

10%

tF

tR

tWL

tI2C_READY

ACK on I2C bus

NACK on I2C bus

I2C bus

STSAFE-A120

Electrical characteristics

DS14609 - Rev 1

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