PIC16F883-ESLASHML datasheet(73/288 Pages) MICROCHIP

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Preliminary

41291D-page 71

PIC16F882/883/884/886/887

4.8

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word Register 1 (CONFIG1). The FSCM

is applicable to all external Oscillator modes (LP, XT,

HS, EC, RC and RCIO).

FIGURE 4-8:

FSCM BLOCK DIAGRAM

4.8.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 4-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

primary clock goes low.

4.8.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

configured before a failure occurs.

4.8.3

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or toggling the SCS bit

of the OSCCON register. When the SCS bit is toggled,

the OST is restarted. While the OST is running, the

device continues to operate from the INTOSC selected

in OSCCON. When the OST times out, the Fail-Safe

condition is cleared and the device will be operating

from the external clock source. The Fail-Safe condition

must be cleared before the OSFIF flag can be cleared.

4.8.4

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

LFINTOSC

÷ 64

31 kHz

(~32

μs)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

clock

switchover

has

successfully

completed.

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