P93U422 datasheet(3/10 Pages) PYRAMID

3 / 10 page

P93U422

Page 3 of 10

Document # SRAM102 REV A

Mode

Output

Standby

High Z

Standby

High Z

OUT Disabled

High Z

Read

OUT

Write

High Z

S(DI)

PLZ (WE)

(8)

PHZ (WE)

(8)

TRUTH TABLE

recovery times by eliminating the “write recovery glitch.”

Reading is performed with chip selct one (CS

1) LOW, chip

select two (CS

2) HIGH, write enable

(WE) HIGH and

output enable (OE) LOW. The information stored in the

addressed word is read out on the noninverting outputs

0 through O3). The outputs of the memory go to an

inactive high impedance state whenever chip select one

(CS

1) is HIGH, or during the write operation when write

enable (WE) is LOW.

An active LOW write enable (WE) controls the writing/

reading operation of the memory. When chip select one

(CS

1) and write enable (WE) are LOW and chip select two

(CS

2) is HIGH, the information on data inputs (D0 through

3) is written into the addressed memory word and

preconditions the output circuitry so that true data is

present at the outputs when the write cycle is complete.

This preconditioning operation insures minimum write

FUNCTIONALDESCRIPTION

SWITCHING CHARACTERISTICS (5,6)

Over Operating Range (Commercial and Military)

Notes: H = HIGH

L = Low

X = Don't Care

HIGH Z = Implies outputs are disabled or off. This

condition is defined as high impedance state

for the P93U422.

Unit

Parameters

PLH(A)

(7)

PLH(A)

(7)

PZH (CS1, CS2)

(8)

PZL (CS1, CS2)

(8)

PZH (WE)

(8)

PZL (WE)

(8)

PZH (OE)

(8)

PZL (OE)

(8)

S(A)

h(DI)

S (CS1, CS2)

h (CS1, CS2)

pw(WE)

PHZ (CS1, CS2)

(8)

PLZ (CS1, CS2)

(8)

PHZ (OE)

(8)

PLZ (OE)

(8)

Description

Delay from Address to Output (Address Access Time) (See Fig. 2)

Delay from Chip Select to Active Output and Correct Data (See Fig. 2)

Delay from Write Enable to Active Output and Correct Data (Write Recovery)

(See Fig. 1)

Delay from Output Enable to Active Output and Correct Data (See Fig. 2)

Setup Time Address (Prior to Initiation of Write) (See Fig. 1)

Hold Time Address (After Termination of Write) (See Fig. 1)

Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)

Hold Time Data Input (After Termination of Write) (See Fig. 1)

Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)

Hold Time Chip Select (After Termination of Write) (See Fig. 1)

Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)

Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)

Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)

Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)

P93U422

Max.

Min.

h(A)

P93U422 데이터시트(PDF) 3 Page - Pyramid Semiconductor Corporation

P93U422 데이터시트(HTML) 3 Page - Pyramid Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10

데이터시트 다운로드

링크 URL