UDA1334ATS datasheet(13/24 Pages) PHILIPS

13 / 24 page

2000 Jul 31

Philips Semiconductors

Product speciﬁcation

Low power audio DAC with PLL

UDA1334ATS

Note

1. The output voltage of the DAC scales proportionally to the analog power supply voltage.

14.2

Timing

VDDD =VDDA = 2.4 to 3.6 V; Tamb = −20 to +85 °C; RL =5kΩ; all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed; note 1.

Note

1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz.

S/N

signal-to-noise ratio

fs = 44.1 kHz; code = 0; A-weighted

100

fs = 96 kHz; code = 0; A-weighted

channel separation

100

PSRR

power supply rejection ratio

fripple = 1 kHz; Vripple = 30 mV (p-p)

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Output clock timing in video mode (see Fig.6)

Tsys

output clock cycle

fo = 12.228 MHz

−

81.38

−

fo = 18.432 MHz

−

54.25

−

tCWL

output clock LOW time

fo = 12.228 MHz

0.3Tsys

−

0.7Tsys

fo = 18.432 MHz

0.4Tsys

−

0.6Tsys

tCWH

output clock HIGH time

fo = 12.228 MHz

0.3Tsys

−

0.7Tsys

fo = 18.432 MHz

0.4Tsys

−

0.6Tsys

Serial input data timing (see Fig.7)

fBCK

bit clock frequency

−−

64fs

tBCKH

bit clock HIGH time

−−

tBCKL

bit clock LOW time

−−

rise time

−−

fall time

−−

tsu(DATAI)

set-up time data input

−−

th(DATAI)

hold time data input

−−

tsu(WS)

set-up time word select

−−

th(WS)

hold time word select

−−

SYMBOL

PARAMETER

CONDITIONS

TYP.

UNIT

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