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CS4344 데이터시트(PDF) 14 Page - Cirrus Logic |
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CS4344 데이터시트(HTML) 14 Page - Cirrus Logic |
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14 / 24 page ![]() 14 DS613F1 CS4344/5/6/8 Figure 9. CS4346 Data Format (Right Justified 24) Figure 10. CS4348 Data Format (Right Justified 16) LRCK SCLK Left Channel SDATA 65 4321 0 7 23 22 21 20 19 18 6543 210 7 23 22 21 20 19 18 32 clocks 0 Right Channel Internal SCLK Mode External SCLK Mode Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period LRCK SCLK Left Channel Right Channel SDATA 654321 0 98 7 15 14 13 12 11 10 6543 210 98 7 15 14 13 12 11 10 32 clocks Internal SCLK Mode External SCLK Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152 Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period |
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