DS684F2

13

CS4352

4.4

De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve scales with changes in sample rate, Fs. The

De-emphasis error will increase for sample rates other than 44.1 kHz

When pulled to VL, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM

pin turns off the de-emphasis filter.

Note:

De-emphasis is only available in Single-Speed Mode.

4.5

Recommended Power-Up Sequence

1.

Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, VQ will re-

main low and VBIAS will be connected to VA.

2.

Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up

sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-

Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.6

Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar-

rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between

digital ground and analog ground, the GND pins of the CS4352 should be connected to the analog ground

plane.

All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted

coupling into the DAC.

4.6.1

Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be placed on each supply pin.

Note:

All decoupling capacitors should be referenced to analog ground.

The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements.

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1

F2

3.183 kHz

10.61 kHz

Figure 6. De-Emphasis Curve