DS658F2

29

CS5345

system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this

case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as

near to the CS5345 as possible, with the low value ceramic capacitor being the nearest. All signals, espe-

cially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the

modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to mini-

mize the electrical path from FILT+ and AGND. The CS5345 evaluation board demonstrates the optimum

layout and power supply arrangements. To minimize digital noise, connect the CS5345 digital outputs only

to CMOS inputs.