1997 Jan 28

18

Philips Semiconductors

Product specification

Data processor for cellular radio

(DPROC2)

UMA1002

Fig.8 Data timing diagrams.

(1) The buffer time depends on whether the first or subsequent words are being loaded.

(2) The system controller should monitor the TXLINE during bit 0, if the status of TXLINE does not change from a HIGH-to-LOW on the rising edge of

TXCLK, then a framing error has occurred. This can be caused by glitches on the clock line or if an arbitration error occurred while the DPROC2

transmit register was being loaded. The system controller should recover the situation by holding TXLINE HIGH and supplying clocks on TXCLK

until TXLINE goes LOW. Then the situation should be treated as a normal channel arbitration failure as described in Section “Reverse Control

Channel Access Arbitration” - “Abort procedure (see Fig.10)”.

(a) DPROC2 to microcontroller link; receive data timing.

(b) Microcontroller to DPROC2 link; transmit data timing.

Where:

handbook, full pagewidth

MBC769

bit 31

bit 30

bit 29

bit 2

bit 1

bit 0

RWIN

t CLK (min)

t

WAIT

RXLINE

RXCLK

bit 39

bit 38

t h

t su

TXLINE

TXCLK

bit 1

bit 0

(2)

buffer clear

DPROC holds TXLINE LOW

during encoder stage

t

WAIT

TWIN

(a)

(b)