CS42432-DMZ datasheet(41/59 Pages) CIRRUS

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DS673F1

CS42432

7.4

Functional Mode (Address 03h)

7.4.1

MCLK Frequency (MFREQ[2:0])

Default = 000

Function:

Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs.

MCLK can be equal to or greater than SCLK.

7.5

MISCELLANEOUS CONTROL (Address 04h)

7.5.1

Freeze Controls (FREEZE)

Default = 0

Function:

This function will freeze the previous settings of, and allow modifications to be made to the channel mutes,

the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the

FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously,

enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

7.5.2

Auxiliary Digital Interface Format (AUX_DIF)

Default = 0

0 - Left Justified

1 - I²S

Function:

This bit selects the digital interface format used for the AUX Serial Port. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options

are detailed in Figures 16-17.

432

Reserved

MFreq2

MFreq1

MFreq0

Reserved

Ratio (xFs)

MFreq2

MFreq1

MFreq0

Description

SSM

DSM

QSM

1.0290 MHz to 12.8000 MHz

256

N/A

1.5360 MHz to 19.2000 MHz

384

N/A

2.0480 MHz to 25.6000 MHz

512

256

N/A

3.0720 MHz to 38.4000 MHz

768

384

N/A

4.0960 MHz to 51.2000 MHz

1024

512

256

Table 5. MCLK Frequency Settings

432

FREEZE

AUX_DIF

Reserved

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