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CS44600 데이터시트(PDF) 13 Page - Cirrus Logic |
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CS44600 데이터시트(HTML) 13 Page - Cirrus Logic |
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13 / 76 page ![]() DS633F1 13 CS44600 SWITCHING CHARACTERISTICS - DAI INTERFACE (VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.) 15. After powering up, the CS44600, RST should be held low until after the power supplies and clocks are set- tled. 16. See Table 1 on page 26 for suggested MCLK frequencies. 17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation. Parameters Symbol Min Max Units RST pin Low Pulse Width (Note 15) 1- ms DAI_MCLK Duty Cycle (Note 16) 40 60 % DAI_SCLK Duty Cycle 45 55 % DAI_LRCK Duty Cycle 45 55 % DAI Sample Rate (Note 17) Fs 32 192 kHz DAI_SDIN Setup Time Before DAI_SCLK Rising Edge tds 10 - ns DAI_SDIN Hold Time After DAI_SCLK Rising Edge tdh 10 - ns DAI_SCLK High Time tsckh 20 - ns DAI_SCLK Low Time tsckl 20 - ns DAI_LRCK Setup Time Before DAI_SCLK Rising Edge tlrcks 25 - ns DAI_SCLK Rising Edge Before DAI_LRCK Edge tlrckd 25 - ns sck h sc kl t t DA I_ S D IN x lrcks t lrc k d t DA I_ S C L K DA I_ L RCK ds t dh t Figure 6. Serial Audio Interface Timing Figure 7. Serial Audio Interface Timing - TDM Mode sckh sckl t t DAI_SDIN1 dh t ds t lrcks t lrckd t DAI_SCLK (input) DAI_LRCK (input) lrcks t MSB MSB-1 |
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