ICS9DB801C

REV C 08/16/07

ICS9DB801C

Eight Output Differential Buffer for PCI Express (50-200MHz)

6

Pin Description for OE_INV = 1

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

25

GND

PWR

Ground pin.

26

PD

IN

Asynchronous active high input pin used to power down the

device. The internal clocks are disabled and the VCO is

stopped.

27

SRC_STOP

IN

Active high input to stop SRC outputs.

28

HIGH_BW#

IN

3.3V input for selecting PLL Band Width

0 = High, 1= Low

29

DIF_4#

OUT

0.7V differential complement clock outputs

30

DIF_4

OUT

0.7V differential true clock outputs

31

VDD

PWR

Power supply, nominal 3.3V

32

GND

PWR

Ground pin.

33

DIF_5#

OUT

0.7V differential complement clock outputs

34

DIF_5

OUT

0.7V differential true clock outputs

35

OE5#

IN

Active low input for enabling DIF pair 5.

1 = tri-state outputs, 0 = enable outputs

36

OE6#

IN

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

37

DIF_6#

OUT

0.7V differential complement clock outputs

38

DIF_6

OUT

0.7V differential true clock outputs

39

VDD

PWR

Power supply, nominal 3.3V

40

OE_INV

IN

This latched input selects the polarity of the OE pins.

0 = OE pins active high, 1 = OE pins active low (OE#)

41

DIF_7#

OUT

0.7V differential complement clock outputs

42

DIF_7

OUT

0.7V differential true clock outputs

43

OE4#

IN

Active low input for enabling DIF pair 4

1 = tri-state outputs, 0 = enable outputs

44

OE7#

IN

Active low input for enabling DIF pair 7.

1 = tri-state outputs, 0 = enable outputs

45

LOCK

OUT

3.3V output indicating PLL Lock Status. This pin goes high

when lock is achieved.

46

IREF

IN

This pin establishes the reference current for the differential

current-mode output pairs. This pin requires a fixed precision

resistor tied to ground in order to establish the appropriate

current. 475 ohms is the standard value.

47

GNDA

PWR

Ground pin for the PLL core.

48

VDDA

PWR

3.3V power for the PLL core.