| 전자부품 데이터시트 검색엔진 |
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ICS9DB102 데이터시트(PDF) 4 Page - Integrated Device Technology |
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ICS9DB102 데이터시트(HTML) 4 Page - Integrated Device Technology |
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4 / 13 page ![]() IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function ICS9DB102 REV F 08/06/07 ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function 4 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo VO = Vx 3000 Ω 1 Voltage HighVHigh 660 850 1,3 Voltage Low VLow -150 150 1,3 Max Voltage Vovs 1150 1,3 Min Voltage Vuds -300 1,3 Crossing Voltage (abs) Vcross(abs) 250 350 550 mV 1,3 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 12 140 mV 1,3 Long Accuracy ppm see Tperiod min-max values 0 ppm1,2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr 30 125 ps 1 Fall Time Variation d-tf 30 125 ps 1 tpd PLL Mode. 135 185 ps 1 tpdbyp Bypass mode 3.2 3.7 ns 1 Duty Cycle dt3 Measurement from differential wavefrom 45 55 % 1 Output-to-Output Skew tsk3 VT = 50% 25 ps 1 tjcyc-cyc PLL mode. Measurement from differential wavefrom 35 ps 1 tjcyc-cycbyp Additve Jitter in Bypass Mode 30 ps 1 1Guaranteed by design, not 100% tested in production. . 3I REF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements Input to Output Delay Jitter, Cycle to cycle mV Measurement on single ended signal using absolute value. mV Average period Tperiod Statistical measurement on single ended signal using oscilloscope |
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