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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ICS1893CFILF 데이터시트(PDF) 79 Page - Integrated Circuit Systems |
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ICS1893CFILF 데이터시트(HTML) 79 Page - Integrated Circuit Systems |
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79 / 126 page  Chapter 7 Management Register Set ICS1893CF, Rev. F, 03/01/07 Mar. 2007 79 ICS1893CF Data Sheet Rev. F - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893CF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • One, the ICS1893CF 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state regardless of the Twisted-Pair Receiver input conditions. 7.13.9 Squelch Inhibit (bit 18.0) The Squelch Inhibit bit allows an STA to control the ICS1893CF Squelch Detection in 10Base-T mode. When an STA sets this bit to logic: • Zero, before the ICS1893CF can establish a valid link, the ICS1893CF must receive valid 10Base-T data. • One, before the ICS1893CF can establish a valid link, the ICS1893CF must receive both valid 10Base-T data followed by an IDL. |
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