P3C1256

Page 6 of 10

Document # SRAM122 REV B

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P3C1256, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance leads that

cause supply bounce must be avoided by bringing the V

planes directly up to the contactor fingers. A 0.01 µF high frequency

capacitor is also required between V

To avoid signal

reflections, proper termination must be used; for example, a 50

Ω test

environment should be terminated into a 50

Ω load with 1.73V (Thevenin

Voltage) at the comparator input, and a 116

Ω resistor must be used in

series with D

Mode

Standby

Standby

D

Read

Write

CE

CE

CE

CE

CE

H

X

L

L

L

OE

OE

OE

OE

OE

X

X

H

L

X

WE

WE

WE

WE

WE

X

X

H

H

L

I/O

High Z

High Z

High Z

High Z

D

OUT

Power

Standby

Standby

Active

Active

Active

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE

CE

CE

CE