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P4C150 데이터시트(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C150 데이터시트(HTML) 1 Page - Pyramid Semiconductor Corporation |
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1 / 11 page ![]() 1 Document # SRAM105 REV A Revised October 2005 DESCRIPTION The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTL- compatible. The RAM operates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds. Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM LCC (L5) DIP (P4, C4, D4), SOIC (S4) CERPACK (F3) SIMILAR Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level. The P4C150 is available in 24-pin 300 mil DIP and SOIC packages providing excellent board level densities. The device is also available in a 28-pin LCC package as well as a 24-pin FLATPACK for military applications. |
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