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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STAC9220 데이터시트(PDF) 21 Page - Integrated Device Technology |
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STAC9220 데이터시트(HTML) 21 Page - Integrated Device Technology |
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21 / 172 page  STAC9220/9221/9223 8-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 21 STAC9220/9221/9223 V 0.96 102706 8-CHANNEL HIGH DEFINITION AUDIO CODEC 1. With +30dB Boost on, 1.00 Vrms with Boost off. 2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. 3. ± 1dB limits for Line Output & 0dB gain, at -20dBV 4. Amplitude of THD+N, measured with A-weighting filter, over 20 Hz to 20 KHz bandwidth. 5. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 8. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. Any Analog Input to ADC (1 KHz Signal Frequency) Crosstalk - -70 - dB Spurious Tone Rejection - -100 - dB Attenuation, Gain Step Size ANALOG - 1.5 - dB Attenuation, Gain Step Size DIGITAL - 0.75 - dB Input Impedance - 50 - K Ω Input Capacitance - 15 - pF VREFout - 0.5 X AVdd - V VREF - 0.45 X AVdd 0.5 V Interchannel Gain Mismatch ADC - - 0.5 dB Interchannel Gain Mismatch DAC - - - dB Gain Drift 100 - ppm/ºC DAC Offset Voltage - 5 20 mV Deviation from Linear Phase - 10 1 deg. All Analog Outputs Load Resistance - 10 - K Ω All Analog Outputs Load Capacitance - - 50 pF HEADPHONE_OUT Load Resistance - 32 - Ω HEADPHONE_OUT Load Capacitance - 100 - pF Mute Attenuation - - - dB PLL lock time - 96 200 µsec PLL (or Azalia Bit CLK) 24.576 MHz clock jitter - 100 750 psec Parameter Min Typ Max Unit |
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