P4C148/P4C149

Page 3 of 10

Document # SRAM104 REV B

Notes:

1. Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to MAXIMUM rating condi-

tions for extended periods may affect reliability.

2. Extended temperature operation guaranteed with 400 linear feet

per minute of air flow.

3. Transient inputs with V

TIMING WAVEFORM OF READ CYCLE

AC CHARACTERISTICS—READ CYCLE

(V

(2)

–100mA, respectively, are permissible for pulse widths up to 20ns.

4. This parameter is sampled and not 100% tested.

5. CE is LOW and WE is HIGH for READ cycle.

6. WE is HIGH, and address must be valid prior to or coincident with

CE transition LOW.

7. Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is

sampled and not 100% tested.

8. Read Cycle Time is measured from the last valid address to the first

transitioning address.

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Read Cycle Time

10

12

15

20

25

35

45

55

Address Access Time

10

12

15

20

25

35

45

55

Chip Enable Access Time (P4C148)

10

12

15

20

25

35

45

55

Chip Enable Access Time (P4C149)

8

10

12

14

15

20

20

25

Output Hold from Address Change

33333

333

Chip Enable to Output in Low Z (P4C149)

22222

222

Chip Disable to Output in High Z (P4C149)

4568

10

14

18

20

Read Command Setup Time

00000

000

Read Command Hold Time

00000

000

Chip Enable to Power Up Time (P4C148)

00000

000

Chip Disable to Power Down Time (P4C148)

10

12

15

20

25

35

45

55

-45

-55

-15

-20

-25

-35

Sym

Parameter

-10

-12